Application-specific integrated circuits (ASICs) are designed to perform a specific function., as opposed to a microprocessor which can be programmed to perform a variety of functions. The major advantages of ASICs are typically lower unit cost and higher performance. ASICs are normally fabricated in some form of complementary metal-oxide semiconductor (CMOS) technology using custom, standard cell, physical placement of logic (PPL), gate array, or field programmable gate array (FGPA) design.
Gate arrays and FPGAs are semi-custom devices which contain a fixed set of gate structures which may be interconnected in a number of ways to achieve a desired logic function. In gate arrays the interconnect pattern is defined by the manufacturer using customized process masks. In FPGAs the interconnect pattern is programmed electrically by the user.
FPGAs generally include an array of programmable function units (PFUs). A PFU may also be called a configurable logic block (CLB) or a configurable logic element (CLE). Each PFU is a small programmable logic block which often includes one or more input lines, one or more output lines, one or more latches, and one or more look-up table (LUTs). There are usually a greater number of input lines than output lines, with each input line being either a dedicated data line or a dedicated control line. The LUT can be programmed to perform various functions including general combinatorial or control logic, read only memory (ROM), random access memory (RAM), or data path functions between the input and output lines. In this manner, the LUT determines whether the respective PFU performs general logic, or a special mode such as an adder, a subtracter, a counter, an accumulator, a register, or a memory cell such as single-port ROM or a single-port RAM. In some instances, the LUT can be used relatively independently of the latches. FPGAs typically contain on the order of 100-1000 essentially identical PFUs.
FPGAs also include a programmable interconnection network that surrounds the PFUs. The interconnection network includes programmable crosspoint switches and metal interconnect segments (routing nodes) for selectively coupling various PFUs. The crosspoint switches are also called programmable interconnect points (PIPs). The crosspoint switches provide signal switching, amplification, and isolation. The metal interconnect segments may be arranged symmetrically about the FPGA's horizontal and vertical axis.
The function of the FPGA is determined by the combined programming of the PFUs and the interconnection network. The user selects the FPGA function by loading a configuration bit stream into the FGPA at power-up or under system control to accomplish this combined programming. Various bits of the configuration bit stream are stored in the FPGA's internal configuration RAM. The configuration RAM is coupled to the LUTs and to the crosspoint switches. Therefore, the configuration bit stream determines the specific function for each PFU as well as the interconnections between the input and output lines of various PFUs, external bonding pads, and other circuitry in the FPGA. The configuration bit stream may initially reside in an electrically erasable programmable ROM (EEPROM), a ROM on a circuit board, or any other storage medium external to the FPGA.
FPGAs may also be defined in terms of programmable logic cells (PLCs) and programmable input-output cells (PICs). The PLCs contain the PFUs, various configuration RAM, and portions of the interconnect network that couple to the PFUs. Thus, various logic functions are performed in the PLCs. The PICs are located at the perimeter of the device, outside the PLCs. The PICs contain input-output buffers, various configuration RAM, and portions of the interconnect network that couple to the bonding pads. Each PIC, for instance, may contain four buffers for interfacing with four bonding pads. Each buffer may be configured as an input, an output, or a bi-directional input-output. Each buffer may also be configured as TTL or CMOS compatible.
FPGAs are further described in U.S. Pat. Nos. 5,386,156; 5,384,497; 4,870,302; U.S. Pat. Re. No. 34,363; and European Patent Specification Publication No. 0 177 261 B 1; which are all incorporated herein by reference.
RAMs include one or more cells (memory units) with each cell storing a single bit of information. Each cell can be accessed for a read or write operation in some fixed amount of time that is independent of the cell's position or address. This distinguishes RAM from serial, or partly serial, access storage devices such as magnetic tapes, drums, and disks. Access times on the latter devices depend upon the address or position of the data. The address, data and control lines associated with RAM collectively constitute one or more ports. Single-port RAMs allow access to memory cells by only one port. Thus, single-port RAMs do not permit simultaneous operations from different addresses. Multi-port RAMs allow access to memory cells by two or more functionally independent ports. Thus, multi-port RAMs permit simultaneous operations from different addresses. Multi-port RAMs include dual-port RAMs, triple-port RAMs, quadruple-port RAMs, and so on. Dual-port RAMs find use, for instance, in buffers, queues, and registers which require constant updating by both read and write operations. Applications for dual-port RAMs include telecommunications channels which receive data from one source (e.g., a line.) and transfer the data to another source (e.g., a computer). In this instance, the line would be connected to a first port, and the computer would be connected to a second port.
PFUs have been devised to implement dual-port RAMs. For example, an N-input LUT may include a 2.sup.N bit bank of memory cells, an N-to-2.sup.N bit decoder, and an output. This provides a single-port ROM, with the configuration bit stream loading the memory, and the decoder selecting the appropriate cell in response to an address signal. To provide a single-port RAM, additional logic is included to write data into the LUT. A dual-port RAM may be obtained, as taught in the prior art, by providing a second N-to-2.sup.N bit decoder for the single-port RAM. The second decoder selects a RAM cell in response to a second address signal. The first and second decoders permit simultaneous access to the RAM cells by separate address signals. In a similar manner, a third N-to-2.sup.N bit decoder may provide a triple-port RAM, and so on.
Unfortunately, the additional decoders are usually dedicated solely to multi-port RAM operation. If a given PFU is not used as a multi-port RAM, then the additional decoder has little or no use. Since a primary purpose of FPGAs is the ability to implement a wide variety of functions, the use of decoders dedicated solely to supporting multi-port RAMs tends to be a costly and inefficient approach.
Another approach to implementing dual-port RAMs in FPGAs has been recently reported in "XC4000E Logic Cell Array Family", Product Preview, by Xilinx, Inc., May 2, 1995, pp. 1-4. In a first mode, a 16.times.2 single-port RAM in a CLB consists of a 16.times.1 single-port "F-RAM" and a 16.times.1 single-port "G-RAM". In a second mode, the 16.times.2 single-port RAM is converted into a 16.times.1 dual-port RAM. In dual-port mode, any operation that writes to the F-RAM automatically writes to the G-RAM using the F-address. A major drawback, however, is that in dual-port mode the G-address can not be used to write to the G-RAM. As a result, the 16.times.1 dual-port RAM has a read/write port using the F-address, but has a read-only port using the G-address.
Accordingly, there is a need for an FPGA which efficiently implements multi-port RAMs which support both read and write operations at each port.